@inproceedings{cheng_fpga21,
author = {Cheng, Jianyi and Wickerson, John and Constantinides, George A.},
title = {Probabilistic Optimization for High-Level Synthesis},
year = {2021},
isbn = {9781450382182},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/3431920.3439455},
doi = {10.1145/3431920.3439455},
abstract = {High-level synthesis (HLS) tools automatically transform a high-level program, for example in C/C++, into a low-level hardware description. A key challenge in HLS tools is scheduling, i.e. determining the start time of all the operations in the untimed program. There are three approaches to scheduling: static, dynamic and hybrid.Static scheduling has been well studied, however, statically analysing dynamic hardware behaviours is still challenging due to the unpredictability due to run-time dependencies. Existing approaches either assume the worst-case timing behaviour, which can cause significant performance loss or area overhead, or use simulation, which takes significant time to explore a sufficiently large number of program traces.In this work, we introduce a novel probabilistic model allowing HLS tools to efficiently estimate and optimize the cycle-level timing behaviour of HLS-generated hardware. Our framework offers insights to assist both hardware engineers and HLS tools when estimating and optimizing hardware performance.},
booktitle = {The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
pages = {145},
numpages = {1},
keywords = {high-level synthesis, static analysis, petri nets, dynamic scheduling},
location = {Virtual Event, USA},
series = {FPGA '21}
}