程健溢 (Jianyi Cheng)

帝国理工学院博士在读

我现在在帝国理工学院的 电路与系统研究组 攻读博士学位。

研究方向
我的研究旨在用形式化方法做出面积小性能高的硬件。我目前的工作主要是优化 高层次综合 (HLS) 的EDA, 其中包括 Xilinx Vitis HLSLegUp, Dynamatic, CIRCT, ScaleHLS  和 Phism.

研究领域:
硬件编程, EDA, 编程语言,静态分析,形式化验证和概率编程。

谷歌学术个人博客 知乎

研究项目

DASS HLS 编译器: 动静态调度高层次综合编译器



调度的定义是将硬件操作分配到时钟周期。它既可以在编译时间中完成(静态调度)从而实现更简单的硬件架构,也可以在运行时间完成(动态调度)从而实现更高的性能。DASS 旨在实现一种全自动并且高效的方法去实现动静态调度相结合的最佳硬件架构。

(发表于 FPGA 2020, TCAD 2021, FCCM 2021, FPGA 2022.)

基于形式化验证的硬件优化



形式化验证采用现有的数学工具去自动证明对象的一个特性,这在证明软硬件的正确性中被广泛使用。这个项目旨在利用形式化验证去优化硬件的面积或者性能。左图的例子是利用形式化验证在不影响运行结果的情况下自动简化多线程硬件里的内存仲裁逻辑。

(发表于 FPGA 2019, TC 2021, FPL 2021, FCCM 2022, FPL 2022.)

基于 MLIR 的软硬件分析和优化



现有的高层次综合平台大多基于例如 LLVM IR 的单一软件抽象层,使得硬件优化的算法不具有可扩展性和定制。这个项目旨在利用 MLIR 多层抽象层表达的优势来优化硬件设计的面积和性能。

(发表于 HPCA 2022, LATTE 2021, FPL 2022.)

学术成果

FPL 2022 高层次综合中基本块之间的动态调度
Jianyi Cheng, Lana Josipović, George A. Constantinides and John Wickerson. Dynamic Inter-Block Scheduling for HLS. In IEEE Int. Symp. on Field-Programmable Logic and Applications, 2022.
[pdf | cite]

FPL 2022 POLSCA: 基于编译转换的多面体高层次综合
Ruizhe Zhao, Jianyi Cheng, Wayne Luk and George A. Constantinides. POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. In IEEE Int. Symp. on Field-Programmable Logic and Applications, 2022.
[pdf | cite]

FCCM 2022 高层次综合中的动态 C-slow 流水线加速
Jianyi Cheng, John Wickerson and George A. Constantinides. Dynamic C-Slowing Pipelining for HLS. In IEEE Int. Symp. on Field-Programmable Custom Computing Machines, 2022.
[pdf | DOI | slides | video | cite]

FPGA 2022 发现并调优动态调度电路中的静态岛屿
Jianyi Cheng, John Wickerson and George A. Constantinides. Finding and Finessing Static Islands in Dynamically Scheduled Circuits. In ACM Int. Symp. on Field-Programmable Gate Arrays, 2022.
[pdf | DOI | slides | video | cite]

FPL 2021 利用内存依赖距离和时延的关系对循环流水线的开发
Jianyi Cheng, John Wickerson and George A. Constantinides. Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. In IEEE Int. Symp. on Field-Programmable Logic and Applications, 2021.
[pdf | DOI | slides | video | cite]

FCCM 2021 高层次综合的概率调度
Jianyi Cheng, John Wickerson and George A. Constantinides. Probablistic Scheduling in High-level Synthesis. In The Proceedings of the IEEE International Symposium On Field-Programmable Custom Computing Machines, 2021.
[pdf | DOI | slides | cite]

TC 2021 多线程综合的高效自动内存分配器
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason H Anderson, John Wickerson and George A. Constantinides. Efficient Memory Arbitration in High-Level Synthesis from Multi-threaded Code. IEEE Transactions on Computers, 2021.
[pdf | DOI | cite]

TCAD 2021 动静态调度高层次综合工具 DASS
Jianyi Cheng, Lana Josipović, George A. Constantinides, Paolo Ienne and John Wickerson. DASS: Combining Dynamic & Static Scheduling in High-level Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021.
[pdf | DOI | cite]

FPGA 2020 高层次综合的动静态调度
Jianyi Cheng, Lana Josipović, George A. Constantinides, Paolo Ienne and John Wickerson. Combining Dynamic & Static Scheduling in High-level Synthesis. In The Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020.
[pdf | DOI | slides | cite]

FPGA 2019 多线程综合的高效自动内存分配器 EASY
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason H Anderson and George A. Constantinides. EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. In The Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
[pdf | DOI | slides | cite]

其他

WRC 2022 Jianyi Cheng. DASS: An Automated HLS Tool that Combines Dynamic & Static Scheduling. In HiPEAC Workshop on Reconfigurable Computing, 2022.
[slides]

FLASHLIGHT 2022 Jianyi Cheng. Optimizing HLS using Petri Nets. In First Workshop on Formal Methods in High-Level Synthesis, 2022.
[slides]

HPCA 2022 基于 MLIR 的可扩展的高层次综合
Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer and Deming Chen. ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. In IEEE Int. Symp. on High-Performance Computer Architecture, 2022.
[pdf]

LATTE 2021 基于 MLIR 高层次综合的 polyhedral 优化
Ruizhe Zhao and Jianyi Cheng. Polyhedral High-Level Synthesis in MLIR. In Workshop on Languages, Tools, and Techniques for Accelerator Design, 2021.
[pdf | DOI | cite]

FPGA 2021 基于概率的高层次综合优化
Jianyi Cheng, John Wickerson and George A. Constantinides. Probablistic Optimization for High-level Synthesis. In The Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2021.
[DOI | cite]

开发工具

DASS HLS 编译器
II 优化器 for Xilinx Vitis HLS
EASY 内存分配优化器 for LegUp HLS

学术服务

程序委员会成员

Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE)

审稿人

IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
ACM Trans. on Reconfigurable Technology and Systems (TRETS)
ACM Trans. on Architecture and Code Optimization (TACO)

学术成果评审(Artifact-Evaluation-Committee)

ACM Int. Conf. on Programming Language Design and Implementation (PLDI)
ACM Int. Symp. on Field-Programmable Gate Arrays (FPGA)
ACM Int. Conf. on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA)

联系方式

邮件: jianyi.cheng17@imperial.ac.uk

9楼,906
电子与电气工程学院
帝国理工学院
南肯辛顿校区
伦敦, SW7 2AZ

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