Postdoc Openings

Automated Formal Hardware Verification

This is a part-time research position (20 hours per week) from Nov 2025 to June 2026. Dates can be flexible.

Hardware verification is often time-consuming, as engineers must manually interpret RTL code and specifications. This project explores techniques to automatically translate software assertions (e.g., assert c == b + c) into hardware properties, thereby assisting the verification process.

Required Skills

• Proficiency in C++ and SystemVerilog
• Experience with HLS tools, e.g., Xilinx Vitis HLS

Preferred Skills

• Experience with SystemVerilog Assertions
• Experience with Microsoft Boogie/Dafny

How to Apply

If interested, please email me your CV along with a short paragraph describing your fit for the role. Feel free to reach out with any questions.