Jianyi Cheng

Ph.D. Candidate at Imperial College London

I am a Ph.D. candidate in the Circuits and Systems group at Imperial College London.

My research aims to produce smaller and faster hardware using formal methods. My current work is mainly focused on high-level synthesis (HLS) tool optimisation, including LegUp and Dynamatic.

My research interests include high-level synthesis (HLS), static program analysis, software verification, dataflow architecture, multi-threaded programs on FPGA and memory architecture optimisation.

Google Scholar: link

Publications

C2 Combining Dynamic & Static Scheduling in High-level Synthesis
Jianyi Cheng, Lana Josipović, George A Constantinides, Paolo Ienne and John Wickerson, in The 2020 Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’20), 2020.

C1 EASY: Efficient Arbiter SYnthesis from Multi-threaded Code
Jianyi Cheng, Shane T Fleming, Yu Ting Chen, Jason H Anderson and George A Constantinides, in The 2019 Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’19), 2019.

Tools

Download EASY >>>

Download DSS >>>

People

Supervisors
Prof. George A. Constantinides
Dr. John Wickerson

Collaborators
Paolo Ienne, Lana Josipović, Jason H. Anderson, Yu-Ting Chen, Shane T. Fleming

Contact

E-mail: jianyi.cheng17@imperial.ac.uk

Room 906, 9th Floor
Department of Electronic and Electrical Engineering
Imperial College London
South Kensington Campus
London, SW7 2AZ

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