Jianyi Cheng

I am a Ph.D. candidate in the Circuits and Systems (CAS) group at Imperial College London, supervised by Prof. George A. Constantinides and Dr. John Wickerson.

My research aims to produce smaller and faster hardware using formal methods. My current work is mainly focused on high-level synthesis (HLS) tool optimisation, including Xilinx Vitis HLS, LegUp, Dynamatic, CIRCT, ScaleHLS and Phism.

My research interests include hardware programming, programming language, static analysis, formal verification and probabilistic programming.

Google ScholarBlog

Projects

DASS HLS Compiler: Combining Dynamic & Static Scheduling



Scheduling is the process of mapping operations to clock cycles. Scheduling can be either done at compile time (static) which can simplify circuitry, or run time (dynamic) which can improve performance. DASS seeks a fully-automated and efficient scheduling approach that combines the best of both worlds.

(Published in FPGA 2020, TCAD 2021, FCCM 2021, FPGA 2022.)

Hardware Optimization using Formal Verification


Formal verification uses automated mathematical techniques to prove the properties of an instance, which has been widely used for verifying the correctness of software and hardware designs. This project seeks a fully-automated approach that uses formal verification to improve the area or performance of hardware designs. The figure on the left is an example of automatically simplifying the arbitration logic of a multi-threaded hardware memory system.

(Published in FPGA 2019, TC 2021, FPL 2021, FCCM 2022, FPL 2022.)

Hardware Analysis and Optimization in MLIR



Existing HLS infrastructures use a single-level software abstraction (e.g., LLVM IR) which restricts the scalability and customizability in hardware design. This project exploits the benefits of a multi-level compiler infrastructure called Multi-Level Intermediate Representation (MLIR) to improve the hardware designs.

(Published in HPCA 2022, LATTE 2021, FPL 2022.)

Publications

FPL 2022 Jianyi Cheng, Lana Josipović, George A. Constantinides and John Wickerson. Dynamic Inter-Block Scheduling for HLS. In IEEE Int. Symp. on Field-Programmable Logic and Applications, 2022. (Best Paper Award Nominee)
[pdf | slides | cite]

FPL 2022 Ruizhe Zhao, Jianyi Cheng, Wayne Luk and George A. Constantinides. POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. In IEEE Int. Symp. on Field-Programmable Logic and Applications, 2022.
[pdf | cite]

FCCM 2022 Jianyi Cheng, John Wickerson and George A. Constantinides. Dynamic C-Slowing Pipelining for HLS. In IEEE Int. Symp. on Field-Programmable Custom Computing Machines, 2022.
[pdf | DOI | slides | video | cite]

FPGA 2022 Jianyi Cheng, John Wickerson and George A. Constantinides. Finding and Finessing Static Islands in Dynamically Scheduled Circuits. In ACM Int. Symp. on Field-Programmable Gate Arrays, 2022.
[pdf | DOI | slides | video | cite]

FPL 2021 Jianyi Cheng, John Wickerson and George A. Constantinides. Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. In IEEE Int. Symp. on Field-Programmable Logic and Applications, 2021.
[pdf | DOI | slides | video | cite]

FCCM 2021 Jianyi Cheng, John Wickerson and George A. Constantinides. Probablistic Scheduling in High-level Synthesis. In IEEE Int. Symp. on Field-Programmable Custom Computing Machines, 2021.
[pdf | DOI | slides | cite]

TC 2021 Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason H Anderson, John Wickerson and George A. Constantinides. Efficient Memory Arbitration in High-Level Synthesis from Multi-threaded Code. IEEE Trans. on Computers, 2021.
[pdf | DOI | cite]

TCAD 2021 Jianyi Cheng, Lana Josipović, George A. Constantinides, Paolo Ienne and John Wickerson. DASS: Combining Dynamic & Static Scheduling in High-level Synthesis. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2021.
[pdf | DOI | cite]

FPGA 2020 Jianyi Cheng, Lana Josipović, George A. Constantinides, Paolo Ienne and John Wickerson. Combining Dynamic & Static Scheduling in High-level Synthesis. In ACM Int. Symp. on Field-Programmable Gate Arrays, 2020.
[pdf | DOI | slides | cite]

FPGA 2019 Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason H Anderson and George A. Constantinides. EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. In ACM Int. Symp. on Field-Programmable Gate Arrays, 2019.
[pdf | DOI | slides | cite]

Other publications or presentations

WRC 2022 Jianyi Cheng. DASS: An Automated HLS Tool that Combines Dynamic & Static Scheduling. In HiPEAC Workshop on Reconfigurable Computing, 2022.
[slides]

FLASHLIGHT 2022 Jianyi Cheng. Optimizing HLS using Petri Nets. In First Workshop on Formal Methods in High-Level Synthesis, 2022.
[slides]

HPCA 2022 Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer and Deming Chen. ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. In IEEE Int. Symp. on High-Performance Computer Architecture, 2022.
[pdf]

LATTE 2021 Ruizhe Zhao and Jianyi Cheng. Polyhedral High-Level Synthesis in MLIR. In Workshop on Languages, Tools, and Techniques for Accelerator Design, 2021.
[pdf | DOI | cite]

FPGA 2021 Jianyi Cheng, John Wickerson and George A. Constantinides. Probablistic Optimization for High-level Synthesis. In ACM Int. Symp. on Field-Programmable Gate Arrays, 2021.
[DOI | cite]

Tools

DASS HLS Compiler
II Prover for Xilinx Vitis HLS
EASY for LegUp HLS

Services

Program Committee Member

Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE)

Reviewer

IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
ACM Trans. on Reconfigurable Technology and Systems (TRETS)
ACM Trans. on Architecture and Code Optimization (TACO)

Artifact Evaluation Committee Member

ACM Int. Conf. on Programming Language Design and Implementation (PLDI)
ACM Int. Symp. on Field-Programmable Gate Arrays (FPGA)
ACM Int. Conf. on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA)

Contact

E-mail: jianyi.cheng17@imperial.ac.uk

Room 906, 9th Floor
Department of Electronic and Electrical Engineering
Imperial College London
South Kensington Campus
London, SW7 2AZ

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