Publications

The best detailed view of my research is from my publications. Here is my (incomplete) list of publications, but there might be a certain time lag. If you want the PDF of one of my papers, please ask.

2025

  1. FPGA 2025
    Latency Insensitivity Testing for Dataflow HLS Designs
    Jianyi Cheng , Lianghui Wang , Zijian Jiang , Yungang Bao , and Kan Shi

2024

  1. FPL 2024
    HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator
    Zhewen Yu , Sudarshan Sreeram , Krish Agrawal , Junyi Wu , Alexander Montgomerie-Corcoran , Cheng Zhang , Jianyi Cheng , Christos-Savvas Bouganis , and Yiren Zhao
    HTML PDF
  2. ICML 2024
    LQER: Low-Rank Quantization Error Reconstruction for LLMs
    Cheng Zhang , Jianyi Cheng , George A Constantinides , and Yiren Zhao
    HTML PDF
  3. ASPLOS 2024
    SEER: Super-Optimization Explorer for High-Level Synthesis using E-Graph Rewriting
    Jianyi Cheng , Samuel Coward , Lorenzo Chelini , Rafael Barbalho , and Theo Drane
    HTML PDF

2023

  1. EMNLP 2023
    Revisiting Block-based Quantisation: What is important for sub-8-bit LLM inference?
    Cheng Zhang , Jianyi Cheng , Ilia Shumailov , George A Constantinides , and Yiren Zhao
    HTML PDF
  2. FPL 2023
    PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration
    Alexander Montgomerie-Corcoran , Zhewen Yu , Jianyi Cheng , and Christos-Savvas Bouganis
    HTML PDF
  3. TC 2023
    Balancing Static Islands in Dynamically Scheduled Circuits using Continuous Petri Nets
    Jianyi Cheng , Estibaliz Fraca , John Wickerson , and George A Constantinides
    HTML PDF
  4. TRETS 2023
    Parallelising Control Flow in Dynamic-Scheduling High-level Synthesis
    Jianyi Cheng , Lana Josipović , John Wickerson , and George A Constantinides
    HTML PDF

2022

  1. FPT 2022
    Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis
    Xuefei He , Jianyi Cheng , and George A Constantinides
    HTML PDF
  2. FPL 2022
    Dynamic Inter-Block Scheduling for HLS
    Jianyi Cheng , Lana Josipović , George A Constantinides , and John Wickerson
    (Best Paper Award Nominee)
    HTML PDF
  3. FPL 2022
    POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations
    Ruizhe Zhao , Jianyi Cheng , Wayne Luk , and George A Constantinides
    HTML PDF
  4. FCCM 2022
    Dynamic C-Slow Pipelining for HLS
    Jianyi Cheng , John Wickerson , and George A Constantinides
    HTML PDF
  5. FPGA 2022
    Finding and Finessing Static Islands in Dynamically Scheduled Circuits
    Jianyi Cheng , John Wickerson , and George A Constantinides
    HTML PDF
  6. HPCA 2022
    Scalehls: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation
    Hanchen Ye , Cong Hao , Jianyi Cheng , Hyunmin Jeong , Jack Huang , Stephen Neuendorffer , and Deming Chen
    HTML PDF

2021

  1. FPL 2021
    Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS
    Jianyi Cheng , John Wickerson , and George A Constantinides
    HTML PDF
  2. FCCM 2021
    Probabilistic Scheduling in High-Level Synthesis
    Jianyi Cheng , John Wickerson , and George A Constantinides
    HTML PDF
  3. TC 2021
    Efficient Memory Arbitration in High-Level Synthesis from Multi-Threaded Code
    Jianyi Cheng , Shane T Fleming , Yu Ting Chen , Jason Anderson , John Wickerson , and George A Constantinides
    HTML PDF
  4. TCAD 2021
    DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis
    Jianyi Cheng , Lana Josipović , George A Constantinides , Paolo Ienne , and John Wickerson
    HTML PDF

2020

  1. FPGA 2020
    Combining Dynamic & Static Scheduling in High-Level Synthesis
    Jianyi Cheng , Lana Josipovic , George A Constantinides , Paolo Ienne , and John Wickerson
    HTML PDF

2019

  1. FPGA 2019
    EASY: Efficient Arbiter SYnthesis from Multi-Threaded Code
    Jianyi Cheng , Shane T Fleming , Yu Ting Chen , Jason H Anderson , and George A Constantinides
    HTML PDF